Synthetic Benchmark Circuits for Timing-driven Physical Design Applications

For the development and evaluation of new algorithms, architectures and technologies, a huge amount of benchmark circuits with suitable characteristic parameters are required. Synthetic circuits are a viable alternative to real circuits for compiling benchmark suites. A major advantage of synthetic benchmark circuits is that full control of the important parameters is provided. In this paper, an existing netlist generation algorithm based on bottom-up clustering of subcircuits according to Rent’s rule is extended to generate circuits that are more realistic than before. The stochastic properties of the Rent behavior are taken into account, and improvements have been made to increase the accuracy of the imposed Rent characteristics. This guarantees a realistic structure of the interconnection topology, which can be adjusted in a controlled manner. A scheme for combinational loop prevention has been augmented with a delay control mechanism, such that they are truly suitable for timing-driven applications. An indirect validation approach is used to verify that existing placement algorithms exhibit comparable behavior for both real and synthetic